VMETRO continues VPX momentum with addition of 3U VITA 46 FPGA Processing Engine

VMETRO, a leader in embedded computing solutions based on standards such as VXS, VPX, XMC and FMC that utilize multi-gigabit serial interconnects, today announced the industry’s first 3U VPX FPGA processing engine with support for the new FPGA Mezzanine Card (FMC/VITA 57) standard, the FPE320.

FPE320 3U VPX Xilinx Virtex-5 FPGA processor board with FMC site
FPE320 3U VPX Xilinx Virtex-5 FPGA processor board with FMC site

VMETRO, a leader in embedded computing solutions based on standards such as VXS, VPX, XMC and FMC that utilize multi-gigabit serial interconnects, today announced the industrys first 3U VPX FPGA processing engine with support for the new FPGA Mezzanine Card (FMC/VITA 57) standard. The FPE320 incorporates the largest available Xilinx® Virtex®-5 FPGAs and an onboard FMC mezzanine site. This combination of high-performance FPGA processing and the flexibility of FMC-based I/O in a air- or conduction-cooled 3U VPX package is ideal for demanding real-time applications such as Electronic Warfare (EW) and Signal Intelligence (SIGINT), Electronic Counter Measures (ECM), and UAV sensor acquisition.

In 3U systems, physical board size has limited the use of large FPGAs with larger I/O mezzanines such as PMC/XMC. With the advent of the FMC I/O mezzanine standard, the largest available Virtex-5 FPGAs can be used in 3U systems because the I/O space requirements are minimized. The FPE320 supports Xilinx Virtex-5 SXT, LXT and FXT FPGAs in the FF1738 package and has a single FMC (VITA 57) mezzanine site for I/O. In addition, the FPE320 provides two banks of DDR2 SDRAM and two banks of QDRII SRAM memory along with four x4 high-speed serial interconnects (16 RocketIO™ GTPs) to the backplane for PCI Express®, AuroraTM, or Serial RapidIOTM and additional user-defined I/Os to the backplane.

Development for the FPE320 is supported by VMETROs FusionXF FPGA development kit. FusionXF is a collection of software and associated HDL functions to aid customers in the development of their FPGA algorithms and logic for VMETROs customer-programmable FPGA products. It is targeted at reducing the design time and optimizing the performance of complex embedded real-time DSP systems comprised of multiple FPGA and PowerPC processors. FusionXF includes a Software Development Kit (SDK) and an HDL Development Kit (HDK). The SDK provides host software support for Windows, VxWorks and Linux. The HDK contains the FPGA interface definitions and HDL functions to build a fully functional FPGA design. Example software and HDL are provided for the interconnects and the external memory with the Virtex-5 FPGA.

The FPE320 is VPX (VITA 46) compliant with .8” pitch and is available in both air and conduction cooled versions.