When half isn't exactly half: 3U vs. 6U VPX
3U VME, once a staple of the architecture, faded from the mainstream many years ago. However, the overall benefits of a 3U format have led architects back to 3U several times over the years, with the latest offering being VPX in both 3U and 6U formats. The trade-offs in choosing 3U are not as simple as “half” of 6U. Thomas explores some of the considerations in selecting a 3U versus 6U VPX format.
The original version of VME created in the 1980s, which eventually was standardized as IEEE 1014-1987, called for both 3U and 6U form factors. The 3U format was popular initially, because there were enough pins on the single 96-pin P1 connector to support the popular 16-bit microprocessors of the era, and the board size was similar to contemporary standards such as STDbus, Multibus II (single), S-100, and others.
However, over time the 3U VME format fell mostly out of favor as address and data bus widths increased, calling for more pins on the backplane. As 32-bit processors became the norm, the 6U format with both P1 and P2 connectors became the de facto size of choice for VME, dominating market offerings. As manufacturers embraced 6U VME more and more, they also realized the benefits of increased real estate for integrating more features on a single board, and created densely packed designs.
In a revisit to 3U format, the CompactPCI specification defined in the 1990s brought a denser connector to the fray with more available pins. It began with a 3U format and later incorporated a 6U format. The 3U version was still somewhat limited by pin availability for I/O in some applications, but has seen fair success.
As developers continue to ask for higher performance and functional density, the need for a 3U format hasn't gone away. This is especially true in light of considerations such as Size, Weight, and Power (SWaP). Given the examples where 3U formats have proven viable, the architects of VME specifications have likewise stepped back to reevaluate a 3U format for their technology.
Serial interconnects are now to the point where speed, reliability, and robustness make them a viable option for board-to-board interconnect. By eliminating the parallel bus constraint - and defining an interconnect scheme leveraging new serial technologies such as Serial RapidIO, Ethernet, and PCI Express - pins can be freed up to support the right mix of data and control plane pins without sacrificing board-to-board bandwidth.
This is exactly the approach called for in VPX, the ANSI/VITA 46 family of specifications. VPX has returned to defining both a 3U and 6U format, allowing designers to choose the best for their application. But the choice is not as simple as it seems on the surface. We learned in grade school that 3 is half of 6, but is 3U half of 6U?
Empirically half, but effectively less
At first glance, a 3U board would appear to be half the size of a 6U board. Viewed from the front panel, this is very true: A 3U front panel is 132 mm long, while a 6U front panel is 265 mm long, and both are the same width. Based on this, it seems logical that a 3U board can contain 50 percent of the functionality of a 6U board.
But a closer look is needed to evaluate the actual board area available to designers on each format. One consideration easy to overlook is the requirement for conduction cooling, with the wedgelocks on the vertical edges of the board. Many potential VPX applications such as UAVs indeed require conduction cooling. Also of consideration is the depth required for the backplane connectors, which consume a considerable amount of real estate. A simplified diagram is shown in Figure 1.
The outline of a 3U printed circuit card is 100 x 160 mm, but with the keep-outs required for the connectors and conduction cooling wedgelocks, the "useful" area is approximately 78 x 148 mm, or 11,544 mm2. The same considerations applied to a 6U outline of 233 x 160 mm result in a useful area of 211 x 148 mm, or 31,228 mm2.
With this reasoning, the mathematical ratio of available real estate on 3U compared to 6U is only 37 percent - not nearly half. This ratio can be further exacerbated by adding some common features:
- PMC/XMC sites - With connectors and mounting features, a mezzanine board consumes significant space on the underlying carrier card.
- Power supplies - Like many slot card standards, VPX boards take a common set of supply voltages and make onboard conversion to voltages needed to support today's modern microprocessors, memory, networking chips, and other devices. These onboard converters are duplicated on each 3U board, just as on a 6U board.
- Large devices - While relatively easy to place on a 6U format, large parts such as microprocessors, host bridges, and FPGAs can consume large portions of a 3U board very quickly. The placement of these devices can also cause constraints in placing and routing the rest of the board.
Taking into account the points above, it is not unreasonable to argue that the effective area of 3U versus 6U is really closer to 33 percent. Thus, a system that could be implemented with three 6U boards would take as many as nine 3U boards, as shown in Figure 2.
As depicted, this means that the 3U systems consume 150 percent of the total volume to deliver the same functional real estate for circuitry as an equivalent 6U system. This should cause many system designers to seriously consider a 6U solution when they thought they would be better off with 3U.
The scale tips back at six
From that perspective of only 33 percent effective useful area, it seems unlikely designers would ever choose 3U formats. But as mentioned earlier, there is a robust market for 3U formats, and programs like the U.S. Army's FCS are specifying 3U VPX in many cases. Why? Because 3U VPX can be the best choice in scenarios such as these:
- Small systems - For systems comprised of six boards or fewer, the scale tips back in favor of 3U. The total size and weight of a system with fewer than six 3U boards - and the smaller subrack and backplane - is less than an equivalent 6U system.
- Rugged systems - Where systems are subjected to extremes of shock and vibration, 3U boards simply have less surface to flex and cause problems.
- Conduction-cooled systems - For systems where conduction cooling is the method used, 3U boards have shorter paths for heat to be conducted out, which makes it easier to get heat from the board to the cold plate than with 6U boards.
- Necessary functionality availability - 3U can in theory offer a finer functional granularity than 6U. For instance, if an application requires one Fibre Channel interface, one MIL-STD-1553 interface, and one Serial FPDP interface, there would be no reason to use a 6U Fibre Channel board with three interfaces, a 6U MIL-STD-1553 board with three interfaces, and a 6U Serial FPDP board with three interfaces if each of these protocols were available in 3U with just a single interface. If an application needs only 1/3 of the functionality of a 6U board, building a system out of 3U boards would be the best choice. However, this argument only holds true in a perfect world where any conceivable function is readily available as a 3U board on the market. In practice, one will find that there are so many more boards to choose from in the 6U format that this easily will end up as the solution of choice.
- Upgrading an existing 3U-based system - The space for the system to go into may not be large enough to accommodate a system of 6U boards.
So don't think 6U can't be used to build small systems
The conclusion is that for designers who are aiming to implement a small system - especially a very rugged, conduction-cooled system - the 3U format has its benefits. But as indicated, designers should keep in mind that for the smallest of systems, with six 3U boards or less, a 6U system with a small number of boards (three and up) may provide a more compact solution. The larger selection of 6U boards on the market also makes it more likely that a COTS solution can be found. The best news for designers is that with VPX, they have a choice of form factors - 3U or 6U - to provide the highest level of functional density for their application. CS