VPX road map
The original work on VPX started in 2004 with the formation of the VITA 46 working group. Since then, many enhancements have been added to the family of standards supporting the VPX architecture. Features such as advanced cooling schemes and connectivity – for RF and optical – have greatly extended the capability of VPX-based platforms, enabling them to be implemented in many high-performance embedded computers.
One of the primary directives of a standards body in the embedded computing space is to ensure that there is a road map in place to guide the technology through a very long product life. Platforms using technology such as VPX can expect to be viable for well over 30 years. Such longevity requires some serious thought behind the road map. In the days of VMEbus, the performance upgrades were relatively straightforward: VME32 became VME64 with a new and backwards-compatible connector that added two rows of contacts; VME 64 became VME 2eSST by clocking data on both edges of the clock, again, with the connector remaining the same. All of this work doubled the data transfer at each step. Things are not as easy with VPX.
Higher data-rate protocols are being designed into VPX systems, enabled by processor technology advancements supporting higher signal speeds and more cores. Newer protocols such as PCIe Gen 4 and 100GBASE-KR4 Ethernet are being implemented and these protocol standards have road maps for higher data rates, in some cases doubling every two or three years. The teams working on the VPX standards monitor these road maps to determine what needs to be done in future updates. Ensuring that the VPX performance road map can accommodate these protocols is vital to the future of VPX.
Communication plane performance
When the VPX connector was standardized under VITA 46.0 in 2006, it supported signaling rates for protocols running up to 3.125 Gbaud with a path toward reaching 6.25 Gbaud. As signaling rates increase above 10 GBaud, the VPX connector solutions need to evolve to support tougher signal integrity (SI) requirements. The VPX working group is now wrapping up the work necessary to boost the communication plane protocol performance to the 10 Gbaud level through advances in board technology and system design that improve SI.
Two efforts, under the VITA 46.30 and VITA 46.31 working groups, have developed standards calling out VPX connectors that support higher data rates, to at least 25 Gb/s – for protocols such as 100GBASE-KR4 Ethernet and PCIe Gen 4. The primary challenge with these speeds is maintaining signal integrity at these speeds. Every single trace, bend, and connection takes an incredible toll on overall SI at these data rates. The latest work focused on improving the SI of the entire signal path.
All of the changes described in the new standards affect the interface between the PCB and the connector, but not between plug-in module to backplane connectors, thus maintaining intermateability with legacy VITA 46.0 connectors. The VITA 46.31 standard defines a higher-performance connector, with short solder tails designed to be soldered into blind vias in the printed circuit boards. This is an alternate approach to VITA 46.30, which uses smaller-diameter-compliant pins at the board termination. VITA 46.30-compliant connectors are part of a complete system, supporting a channel with SI definitions per VITA 68.2 standards. Both of these documents are under review by the respective working groups. Other alternative footprint connectors may also be standardized in the future as improved methods emerge to address the SI challenge.
What does this mean for VPX? In short, a huge boost to bandwidth: First-generation products were capable of up to 10 Gb/s per lane. Second generation is 2.5 times faster, supporting up to 25 Gb/s per lane. The maximum number of differential pairs, or lanes, for 3U and 6U modules remains unchanged at 64 and 192 lanes, respectively. This update adds tremendous headroom to performance while still maintaining compatibility with no architectural changes required. (Table 1.)
Industry-leading I/O density
The VPX road map includes much more than improving the switched fabric performance capability of the communication channels. VPX is the highest I/O density slot card solution available anywhere. Space is reserved for coaxial and optical connections between plug-in modules and backplanes. Over the past few years, tremendous amounts of work have been performed to add and increase the coaxial RF I/O capability and the optical capability of VPX. A particular focus has been placed on improving the blind mate capability between plug-in modules and backplanes to improve serviceability of VPX systems. (Figure 1.)
VPX is extremely popular in high-end sensor applications that deal with large amounts of data and challenging operating environments. The high bandwidth capability and rugged packaging options work well with both stationary and mobile applications. These sensors frequently require RF connectivity via coax to the computing platform. The VPX working groups saw this need early and developed the VITA 67 standards for RF connectivity to address these needs. The initial solutions defined a standard that could support up to four RF contacts in a half module at a maximum 26.5 GHz.
Issues with cabling have kept the working group focused on improved solutions. VITA 67.1 and VITA 67.2 allow only for a cable termination on the plug-in module’s contacts. Routing cables to another connector on the plug-in module can be difficult. The driving objective of the most recent effort was to allow fixed contacts on the plug-in module and spring-loaded contact action on the backplane. This functionality allows for alternate packaging of the modules, such as edge launching RF contacts directly from the boards, potentially eliminating all cables to the plug-in module. The primary goal of the working group is to build upon the framework laid out in earlier standards for detailing blind mate analog interfaces.
Because the industry has progressed since the initial VITA 67 standards, the need for higher contact densities has arisen. In addition to the physical-space reductions realized by eliminating cable management, the VITA 67.3 backplane modules further increase space efficiency by taking advantage of the full 1.00-inch slot pitch. The contact position within the housings are no longer constrained to the fixed 2 by 2 and 2 by 4 arrays for greater flexibility, up to 12 SMPM contacts.
The VITA 67.3 standard was written with future expansion and backwards compatibility in mind. The initial contacts available are SMPM, but the current draft revision is adding alternate higher-density RF interfaces: SMPS and NanoRF.
The final vision of this working group is the integration of coaxial RF and optical contacts within a single module. This motivation is supported by the continuous drive to optimize the size, weight, and power of the VPX architecture. This is of special importance in 3U applications where backplane I/O is a more limited resource. Sharing the I/O module makes the best use of the available space while providing the flexibility designers require.
To truly reach the next plateau of I/O performance, one has to look to optical connectivity. Optical has many benefits over copper, which is nearing its bandwidth limits. Fortunately, VITA members had the vision to start developing optical interconnects for VPX under the VITA 66 working group several years ago. This work defined optical connections for VPX modules that are widely used in high-speed data paths.
More effort continues as the working group looks for ways to improve the connector interfaces and to add more fibers to the reserved I/O space on VPX modules. The latest efforts are concentrated on increasing the fiber count to 72 and adding spring-loaded contacts. VITA 66.5, “VPX: Optical Interconnect, Spring-Loaded Contact on Backplane,” defines an interface compatible with VITA 46 containing blind mate optical connectors with fixed contacts on the plug-in module and floating displacement on the backplane.
VITA 66.6, “VPX: Optical Interconnect, Half-Width MT Variant, Spring-Supported Ferrules in Both Backplane and Plug-In Module Connectors,” defines an interface compatible with VITA 46 containing blind mate optical connectors, where the connector modules on both the backplane and plug-in module contain spring-supported MT ferrules.
As the road map for optical improves, the headroom is there for tremendous bandwidth. VITA members continue to vigilantly work on technology that may someday enable a practical backplane capable of optical connectivity between slots.
Summary of working groups
VPX is the only blind mate plug-in module standard that supports high-speed serial, coaxial RF, and optical connectivity to a backplane in the embedded computing space. The efforts by the VITA working groups are doing everything possible to improve the performance and functional density of these connectivity options to ensure that VPX continues to be the premier plug-in module solution. In addition, there are several other working groups that are applying the same diligence to standards for power supplies, high-speed mezzanines, and chassis I/O for critical embedded systems.
OpenVPX is the key to tying together the complex VPX architecture. New profiles will be defined that determine the multitude of data path and I/O combinations possible with VPX. Old profiles will be replaced as new ones emerge to take their place. Staying involved in the process is going to be key for companies to stay abreast of future developments.
Connector modules – designed with overarching VPX compliance in mind – are included in new VITA 65 OpenVPX slot profiles. These slot profiles will support an ever-evolving architecture without ever needing to alter the backplane. Payload plug-in modules could be replaced as new capabilities, integrated within a slot, require additional contacts with different arrangements. The upgrade is as simple as replacing the existing backplane connector module with the vender-provided replacement.
Engineering for signal integrity is an absolute must as we continue to bang against the ceiling of copper transmission mediums. We can no longer afford to take shortcuts of any kind and must continue to look at the entire data path as a complex system that needs total optimization to get the required quality of a signal at tomorrow’s data speeds.