Using the updated VITA 65 Standard to build faster high performance systems
Over the past five years, 3U OpenVPX has been the architecture of choice to implement rugged military electronic systems. Application areas include Command, Control, Communications, Computers, Intelligence, Surveillance and Reconnaissance (C4ISR), Electronic Warfare (EW), radar, and network communications. Current technology roadmaps show that signaling rates for PCIe and Ethernet are rapidly increasing and that the mentioned applications are sure to utilize all of the incremental bandwidth.
Rates supported by new single board computers (SBCs) and Ethernet switches now require backplanes to operate at 8 G/T per second for PCIe Gen 3, and up to 10 Gbaud for 10GBASE-KR Ethernet. In the case of Ethernet, the rates have increased from 3.125 Gb to 10.3125 Gb per lane. To address this significant speed increase, new backplane designs are required.
VPX adapts to a changing industry
Technology trends are also driving changes to the OpenVPX standards. New signaling rates of 8 Gb/sec for PCIe Gen3, and 10 and 40 Gb/s for Ethernet are addressed in the third major release of OpenVPX, which is now comprised of two documents - VITA 65.0 and VITA 65.1. The primary specification information is contained in VITA 65.0, with additional Slot and Module definitions moved to VITA 65.1 In addition to the updates for PCIe and Ethernet protocols, other necessary features included in the specification’s update include:
- Backplanes supporting high speed Control and Data planes
- Radial clock lines to provide a means for more accurate skew-adjusted clock
- A defined timing Board profile, SLT3x-TIM-4S16S1U2U1H-14.9.1-n to allow a central source of radial clock (Figure 1)
- Ref Clock increased from 10 MHz to 100 MHz
- New I/O connectors are addressed with VITA 67.3, allowing for new connector apertures supporting both RF and fiber optic I/O using MT ferrules
- High power VITA 62 power supply slots
Standards that drive the use of the new VPX features include the U.S. Army’s CMOSS (C4ISR/EW Modular Open Suite of Standards). In order to test many of these new features, a backplane profile (BKP3-TIM12-15.3.6-n) has been created that addresses this CMOSS architecture (Figure 2).
Backplane and connector technologies critical to program needs
Actual program needs will address specific backplane topologies, which may have reduced a slot count. The topology diagram at the top of Figure 3 shows the presence of two primary domains. Note that most of the interconnects between slots are accomplished via Ethernet. The backplane supports rates from 1 GBASE-KX up to 40 GBASE-KR.
New connectors, which address the VITA 67.3 standard, can now be implemented in the design of VITA 65.0 backplanes. This allows new connector apertures to adapt to evolving connector placements, which can be used to implement radio-frequency (RF) payloads, timing cards, and RF switches.
The architecture also includes the use of expansion plane connections from standard SBCs via PCIe, shown in two groups as Slots 3, 4, and 5 as well as Slots 8, 9, and 10 in Figure 3 on following page.
The new I/O scheme allows mixed I/O including RF and optics. In this example, the payload slots are fitted with VITA 67.3 combo connectors that support up to four RF connections, and one fiber optic connector, with up to 12 individual fibers. VITA 67.3 addresses similar I/O configurations supported by VITA 67.1, VITA 67.2, and VITA 66.4. In addition to the I/O, Slot profiles now describe the interface to new high-speed Ethernet switches supporting Gigabit – and 10 Gigabit – Ethernet rates.
Growing supplier ecosystem and support
VPX suppliers will build VPX boards that conform to the new OpenVPX profiles. Vendors, such as Elma Electronic and others, will address deployment backplanes built for high-speed data transmission and newly introduced profiles. In fact, a 12-slot backplane has recently been designed, built and tested to support a variety of Slot profiles for Payload (SBCs), Peripheral (high speed network switches) and Storage. With options to allow for the latest RF and fiber optic interconnects, this newest, major release of VITA 65.0 (VITA 65.x-2017) allows rear I/O transition of analog and fiber optic high density signals to be passed through the backplane.
Interoperable high-speed system architectures
The third release of the OpenVPX standard will allow system designers to build the latest high speed systems using the next generation of SBCs, switches, and backplanes. The updated standard supports the transition to embedded 10 Gbit Ethernet, supports new radial clock techniques necessary for high performance analog and digital systems, and OpenVPX provides the module and slot profile definitions to support open systems development as well as a means to develop standard, interoperable, off-the-shelf payload modules.