Power.orgís new architecture roadmap: Upscale with more cores

Q&A with Fawzi Behmann, Power.org

1While x86 processors continue to creep into VME backplanes for command and control applications, PowerPCs still do most of the heavy lifting in avionics and mission-critical boxes. But Intel and AMD’s onslaught of multicore processors hasn’t gone unnoticed by the purveyors of Power Architecture devices. Our recent discussion with the chair of Power.org’s Marketing Committee reveals multicore plans, along with a much-needed diet of lower power options. Edited excerpts follow.

VME: Please remind our readers what Power.org's mission is and how it accomplishes that.

BEHMANN: The mission of Power.org is essentially to develop, enable, and promote Power Architecture technology as the preferred open standards hardware for the embedded electronics industry. We have technical committees, marketing committees, and operation committees. We have bylaws and policies in place, along with established work plans. We also offer customers a choice of supplier not only on the processor side but also regarding the operating system supplier of choice for testing, debugging, and simulation. Finally, we have a great opportunity to collaborate and innovate with several thousands of developers associated with Power Architecture. Efforts are underway in developing and promoting a compelling ecosystem that reflects a great level of collaboration and innovation.

VME: Which specifications or recommendations have been released or are in the works at Power.org?

BEHMANN: There are three highlights surrounding one of our major focal points: the Instruction Set Architecture [ISA] roadmap. We have updated that with two revisions so far, including 2.04, which was passed in May 2007 and encompasses additional new facilities including support for virtualized partition memory, along with virtual page class keys.

Then there's 2.05, announced in September 2007 and primarily focusing on enhancing the ISA of server architectures and providing additional capabilities such as floating point facilities, power management, and new instructions supporting aspects like computation efficiency and memory management.

In 2008, though, we're working on the third ISA-related specification, 2.06, which focuses on the ISA for the embedded networking space, in terms of challenging requirements. Embedded space is really constrained by power consumption and increasing performance demands. So we are looking to things such as multicore capabilities and embedded virtualization.

VME: Any other focal points besides the ISA roadmap?

BEHMANN: Besides ISA, another key area is power, and Power.org is producing what's called ePAPR, a specification that defines standard interface between the boot programs and client programs for single core and multicore processors. ePAPR is the foundation of our multicore hypervisor work. What it does is establish a common methodology and procedure for device rebooting and also helps in building a platform for software interfaces. We're actually going to release version 1.1 this year.

Other key working areas include our new low- to high-end performance Power Bus Strategy Report, which looks at comparisons between the different technologies and bus connectivity and multiprocessing cores. We are also working on the Common Debug Interface (CDI) specification, which helps establish a common environment so that tool vendors do not have to develop multiple SW/HW configurations for each processor.

VME: Power Architecture faces a lot of competition from much "younger" technologies such as x86 processors, but is the latest really the greatest?

BEHMANN: Not really. Power Architecture came into existence in the '80s, and it's really carved a space by itself in the marketplace. Power Architecture spans many market segments and, therefore, you would see it in many different applications like communications, wireless infrastructure, storage, industrial, automotive, and aerospace and defense. What's made it strong is really the technological leadership, which helped in building its strong base and facilitating this market growth.

Regarding x86, though, Power Architecture has a pure, higher performance in terms of the device. Power Architecture processor speeds can range from 50 MHz all the way to close to 2 GHz. That's why we can span from the low end to the high end of the market, providing flexibility and scalability and staying feature rich. So essentially the features are optimized for the target market.

VME: In what way do you see Power Architecture evolving in the next five years?

BEHMANN: The Internet is driving a lot of scalability. We see wireless and mobility driving a lot of growth. Convergence and advancement in technology are enabling a new class of services for multimedia broadband rich content designed to enhance end user experience. This puts demand on increase on bandwidth and in turn scalable performance. And certainly we see scalable IP-based products helping scale the network. All of these things collectively are really causing growth in terms of adoption of the right process technologies; therefore, the devices continue to shrink and yet face the challenge to also become higher in performance, competitive in price, and feature rich. Power.org and Power Architecture are prepared to address this growth with major investment in multicore scalable platforms to address the new class of services. So, these are all key challenges that we want to conquer in next-generation type devices with advanced process technology such as 45 nanometer and then going further down the line with that.

VME: How does Power.org intend to keep up with the evolving market, then?

BEHMANN: Overall Power Architecture should see a greater adoption. One thing we are doing to facilitate this more widespread adoption is to initiate collaborative programs with universities, making Power Architecture available as curriculum and providing hands-on reference design so that Power Architecture-skilled graduates become more in demand in the marketplace in years to come. We would also like to continue to build and enlarge the community in terms of third parties, partners, and developers to implement methods that are also market focused.

VME: So, generally speaking, which trends are strongest in today's market, though?

BEHMANN: Although we continue to see Moore's law in action in terms of silicon reduction and increased performance, we may stop witnessing Moore's law beyond 2020. The challenge is to increase performance within a certain power budget to meet increasing demands for high, rich broadband content and services.

VME: So what is the answer to Moore's Law saturation?

BEHMANN: In the embedded networking space where power is a major constraint, having more than one processor that can achieve the next higher level of performance is key. Plus you need some level of assistance through accelerators and an environment that supports the development and the simulation of silicon functionality and timing. Also important is collectively having the software enablement capabilities to support things like multicore.

Additionally, beyond the challenge in the embedded networking space is collaborative supercomputing. I just returned from the Mobile World Congress in Barcelona, where I had the opportunity to visit the Barcelona Supercomputing Center. There, I learned of some major research conducted using over 10,000 large-scale Power Architecture processors simultaneously on a major space project. So the future is bright, and Power Architecture will have a major role to play in coming decades.

Fawzi Behmann is chair of the Marketing Committee at Power.org, where his responsibilities include budgeting, planning, and executing Power.org activities. He also serves as director of strategic marketing for the Networking Systems Division within Freescale's Networking and Multimedia Group. As part of Freescale's Technical Forum Advisory Committee, he coordinates the networking technical content for Freescale networking's international events. Fawzi also chairs the networking System Drivers Working Group at ITRS (International Technology Roadmap for Semiconductors). He received his Bachelor of Science with Honors and Distinction from Concordia University, Montreal, a Master's degree in Computer Science from the University of Waterloo, and an Executive MBA from Queen's University School of Business in Kingston (Canada). He can be reached at fawzi.behmann@freescale.com.

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