Overcoming backplane access limitations in OpenVPX

While the connectors chosen for OpenVPX (VITA 65) have many good features, they are not offered in versions to allow designers easy access to backplane signals. This has necessitated the development of Rear Transition Modules (RTMs), which are often custom and certainly are not universal on all slot profiles. These RTMs are often large and restrict the access to signal points on adjacent slots for concurrent development and test activity.

Because OpenVPX is a point-to-point architecture, backplane design is contingent on the number of cards; the I/O architecture is also driven by the number and location of cards. During development, it is often not possible to finalize the board selection until later in the evaluation phase. This creates a dilemma for program managers who do not want to fund the development of multiple custom backplanes to support internal development. In addition, the evaluation process required to settle on a backplane design adds precious time to the design cycle.

A cabling system has been developed that allows designers access to any point or points on the OpenVPX backplane without an RTM. The cabling system is organized in familiar OpenVPX “pipes” and facilitates the movement of these signals from slot to slot or slot to I/O. Utilizing wafers similar to the ANSI VITA 46/65 approved TE Connectivity MultiGig RT2 connector system, this cabling system is capable of supporting maximum specified ANSI VITA 46/65 data rates of 6.25 Gbaud over 30 gauge coax cable.

Reconfigurable cables

This wafer-based cabling system can be reconfigured by the end user to address changing requirements. As shown in Figure 1, a fat pipe cable (eight differential pairs) carrying InfiniBand can be snapped apart and reapplied to form two thin pipes (four differential pairs each) to carry Ethernet from slot to slot or from a slot on the development backplane to a slot on a separate VPX (VITA 46) system.

21
Figure 1: Cable fat pipe hookup between two separate backplanes
(Click graphic to zoom by 1.9x)

InfiniBand, Serial RapidIO, Ethernet, and PCIe are all high-speed fabrics that can utilize this cabling system from slot to slot or from slot to I/O with the appropriate connector. Implementation using RJ45, CX4, USB, SATA, and eSATA are some of the choices for the system developer.

Using these cables does not inhibit access to adjacent slots and provides limitless access to every point on the VPX backplane. Not only do these cables support all 3U and 6U VPX backplanes, but they are ideally suited to support power/ground development backplanes. And various wafer-to-I/O connector solutions provide designers with the flexibility needed to move fabrics to desired endpoints.

Various wafer options include power wafers for P0, wafers with hookup wire for user-defined options, and wafers for single-ended slot profiles.

This cabling system offers ruggedized options to developers who face last-minute changes to deployable systems or where the volume of systems purchased does not justify custom backplanes.

VPX backplane diagnostics

OpenVPX backplanes have channel requirements defined in ANSI/VITA 46 and ANSI/VITA 65 and the emerging VITA 68 (VPX Compliance Channel) standard. This wafer cable system contains wafers that have SMAs attached to facilitate rapid access to signal points for measurement of crosstalk; they can also access signals from slot to slot to check Tx quality and skew. It takes only a few seconds to relocate the wafers to check a second channel. The signal integrity of these assemblies is adequate for detailed analysis of these tests:

  • Insertion loss: <2.5 dB up to 5 GHz
  • Return loss: <10 dB up to 5 GHz
  • Connector impedance: 100 +/- 10% at 100 ps rise time (20 - 80%)
  • Within pair skew: <3 ps ft
  • Time domain crosstalk: <4% at 40 ps rise time (-20 to +80%) from multiple aggressors

Easing OpenVPX design, hastening time to market

The push by many agencies and primes for continued expansion of open systems has energized VPX as a leading-edge standard where high-density computational power is required. The development and production of this VPX PLUS cabling system has eased the design, test, and development of OpenVPX cards and systems and provided developers with a tool that, in some instances, has no alternate in the OpenVPX ecosystem. The VPX PLUS cabling system consequently enables system designers to rapidly overcome development hurdles and forgo using an RTM.

Robert K. Evans is a consultant in the electronic component marketplace and has an extensive background in product development in the interconnect, passive, and electromechanical device marketplace. Contact him at robert.evans@rkevans.com.