Hybrid radar and electronic warfare architectures

5The Electronic Warfare (EW) market is increasingly diversified across almost every area of defense spending. Despite budget restraints, the market expects growth in the EW domain driven by the trend of EW systems to form a larger part of military activity. New technology offers engineers of EW or Electro-Optical/Infrared (EO/IR) systems the possibility to use remote high performance sensor modules using Gigabit/10 Gigabit serial interfaces to transmit their data sample flows. To manage and process this huge amount of data, engineers must define new, innovative, and open system architectures.

There are two primary technology disruptions influencing the design of Electronic Warfare (EW) systems. The first disruption stems from the latest generation of sensors: high definition daylight or infrared GbE/10 GbE cameras, as well as large antenna arrays for radars with very large output data flows. These sensors are now entering into the surveillance and intelligence space, gathering payloads for Unmanned Aerial Vehicles (UAVs) or Unmanned Ground Vehicles (UGVs), which operate in harsh and tightly-packed environment conditions, installed in remote locations away from the processing units. According to market and technology forecast consultancy ElectroniCast in Aptos, CA, the global defense market for sensors is growing at a double-digit rate behind only energy and smart infrastructures.

The latest generation of extremely powerful FPGAs is the second technology disruption. They can perform massive parallel processing operations, more than 5,000 GMAC/s (Giga Multiply-Accumulate per second) for the Xilinx Virtex-7. They are also better equipped for low power consumption (up to 10x lower) when compared to equivalent CPUs or GPGPUs on integer processing. They also feature huge communication bandwidth improvements, up to 2.76 Tbps for the Virtex-7.

These technology disruptions influence engineers to reconsider existing architectures and to look for new and innovative solutions to capture, transmit, and process the huge streams of data sent from multiple high-speed sensors.

Communication with high-speed sensors

The hybrid OpenVPX architecture in Figure 1 illustrates an innovative approach for building high performance EW platforms. The architecture has a Data Processing Cluster connected via a switchblade to a Signal Processing Cluster. In compliance with the OpenVPX framework, it enables processor and FPGA modules to be connected via high-speed PCIe x 4 links for the data plane and GbE 1000BASE-KX links for the control plane.

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Figure 1: Hybrid OpenVPX architecture with two clusters.
(Click graphic to zoom by 1.9x)

Gigabit and 10 Gigabit serial links connecting the sensors to the processing units implement various switch fabric protocols such as serial FPDP, 10 GbE, Aurora, or serial RapidIO. They transport data over copper or optical cables. However, optical is gaining favor in many applications. Optical cables are lighter, free from EMI radiation, and are EMI resistant, which enables them to avoid interferences inside space-restricted unmanned vehicle systems. Single mode fiber cables can collect data from large antenna arrays or from widely spaced antennas at distances greatly exceeding the capability of copper links. For these reasons sensor designers favor optical links.

To illustrate a typical system, a selection of Interface Concept modules will be used as examples. Sensors with optical links can be connected to the hybrid architecture in two ways. The first solution involves an XMC (Figure 2) with dual QSFP+ (Quad Small Form Factor Pluggable) connectors. This XMC can be plugged into a central position on a hybrid PCIe/Ethernet switch. In this case the PCIe protocol is used for the optical link.

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Figure 2: IC-QSFP-XMCa.
(Click graphic to zoom by 1.9x)

The second solution is using a dual QSFP+ FMC (FPGA Mezzanine Card) as shown in Figure 3. The FMC is plugged into an FPGA module in the Signal Processing Cluster. Protocol-dependent firmware is instantiated into the FPGA, allowing it to capture the data stream from the FMC.

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Figure 3: IC-QSFP-FMCa.
(Click graphic to zoom by 1.9x)

The FMC features two QSFP cages, each one able to receive a four optical fiber QSFP+ interface. Each of these QSFP+ interfaces allows communication on four full-duplex lanes at up to 10 Gbps per lane, depending on the maximum data rate achievable on the FPGA transceiver interface. This can be accomplished at a distance up to 100 meters with multimode 850 nm fiber. A total of eight SERDES run to the FMC connector interfacing the signal processing module. The FMC design includes an onboard microcontroller that manages the QSFP interfaces through an I2C bus and a clock synthesizer through a SPI bus.

By using one of these two methods, the EW hybrid architecture system can accommodate the high stream of sample data from the sensors. The usual first step of signal processing begins with performing massive parallel algorithms on the sample data. These algorithms can be discrete Fourier transforms (for spectral analysis, data compression, or partial differential equations), Cooley-Tuckey fast Fourier transforms, multidimensional discrete cosine transforms, filtering, or beam forming. For this step, designers use the parallel processing power of the fastest high-end FPGA technology in FPGA modules slotted into the Signal Processing Cluster of the hybrid architecture.

Front end processing FPGA modules

The OpenVPX module IC-FEP-VPX3c is an example of a Xilinx Virtex-7 based module for signal processing. An IC-QSFP-FMCa routes eight lanes of data through two quad GTX interfaces, after optical to electrical conversion on the receive side and before electrical conversion on the transmit side.

Behind the FPGA transceivers, middleware is installed to implement the serial fabric protocol of choice, sFPDP, 10 GbE, Aurora, or PCIe.

Relevant algorithms in the FPGA process the data samples received through the optical interfaces using the DSP resources of the Virtex-7. The processing results may be stored in the two high bandwidth DDR3 banks, each one having a 64-bit wide interface. The size of these memory banks (2 GB each) and the width of their interface allow massive real-time data processing before transferring to other parts of the system. The integration of several of these powerful FPGA modules enables the building of very high performance processing systems.

The next step consists of moving this data from the FPGA DDR3 memory to other memory in the system through high-speed links over the backplane. The hybrid architecture allows data plane Fat Pipe communication between the different payloads. In order to move data from memory to memory between different modules on the VPX data plane, DMA engines have to be implemented and used. Interface Concept has developed multi-channel DMA engines that are instantiated into the Virtex-7 FPGAs of the modules, enabling moving data on the data plane and through the PCIe protocol from remote processors in the system.

The IC Cometh4410a hybrid switch (Figure 4) is a non-transparent bridge designed to avoid root complex issues. The switch uses its own DMA controller to move data over the VPX data plane from the DDR3 memories of any FPGA module of the Signal Processing Cluster to the DDR3 memory of any processor slotted into the Data Processing Cluster.

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Figure 4: Cometh4410a hybrid switch.
(Click graphic to zoom by 1.9x)

These DMA engines are able to move data at a rate of 1.5 Gbytes/s on a PCIe x 4 link in Gen2. That rate comes close to the theoretical data throughput limit when including PCIe communication layer overhead and 8B/10B encoding. These DMA engines are driven by CPU processors that are connected to the FPGA modules or that are on the FPGA module itself (in the case of the 6U form factor).

The reference design delivered with the product contains the DMA engine IP able to perform these high-speed memory data transfers. To ease the development work on these hybrid architecture systems, a software package called Multiware provides a high-level abstraction in order to provide the designer with services such as Virtual Ethernet over PCIe, shared memory, and message synchronization with DMA-powered transfers between FPGA modules and CPU modules or between different CPU modules. The designer can then focus on the application without the burden of tedious software writing.

With the Multiware software package and hardware hybrid architecture, developers can quickly design advanced high performance radar and EW systems for next-generation defense applications.

The combination of VPX, latest generation FPGAs, optical interconnects, and Interface Concept intellectual property provide designers with an excellent platform for building robust signal and data processing platforms.

Thierry Wastiaux is Senior Vice President of Sales at Interface Concept, a European manufacturer of electronic embedded systems for defense, aero, telecommunications, and industrial markets. He has 25 years of experience in the embedded systems and telecom market, having held positions responsible for operations, business development, and general executive management. Prior to joining Interface Concept, he was responsible for the operations of the Mobile Communication Group and the Wireless Transmission Business Unit at Alcatel-Lucent. He holds an M.Sc. from France’s Ecole Polytechnique. Readers may contact M. Wastiaux at twastiaux@interfaceconcept.com.

Interface Concept 215-956-1200 www.interfaceconcept.com