FPGAs impact on next generation sensor digital signal processing

Sensors of all types are the eyes, ears, nose, and antennae of the military commander whether they are integrated into a main battle tank, a submarine, a helicopter, or a tactical aircraft. Sensors can be active (laser range-finder, radar, and sonar), or passive (optical, infra-red, sonar, and radio frequency). Individual sensors are used to identify an individual target for the soldier or to identify and track an enemy aircraft. Multiple sensor platforms are used to create a complete air, land, and sea situational picture for the battle commander. Regardless of where in the electromagnetic, visual, sound, or organic spectra the sensor is operating, the received signals are processed digitally and the resulting data is used to construct an interpretable model that allows the system controllers to take the appropriate action.

Dedicated Digital Signal Processing devices have evolved alongside conventional microprocessors for many years. DSP devices were optimized to perform DSP application operations such as Fast Fourier Transforms (FFTs) and the rapid transfer of data blocks between multiple devices. But they were very poor general-purpose processors. This resulted in the development of hybrid systems consisting of optimized front-end DSP processors, and multiple back-end general-purpose processors for system management, communication, and display functions. The gate count and speed of DSP devices developed rapidly, which made the use of an increasing number of DSP devices economically viable. This development, together with improved Analog-to-Digital speed and conversion accuracy, increased overall system sensitivity and hence the quality of the received data. In addition to increased sensitivity, more channels are being introduced into the sensor systems for either full 3D coverage in the case of radars and sonars, or for increased coverage of frequency bands for digital radio, signals intelligence, or electronic warfare systems.

The development of the PowerPC architecture and the AltiVec vector processor by Motorola signaled the convergence of general purpose processing and DSP into a single device. The AltiVec executes floating point FFTs as fast as competing specialized DSP devices, and its PowerPC processor means it can be programmed easily using COTS tools that are currently available from multiple vendors. PowerPC with AltiVec is now the established processor of choice for embedded DSP processing. In VMEbus form it can be used singly (as a SBC), or in higher density dual and quad configurations at the board level. With the addition of suitable switched fabrics for very high speed movement of data between processors, a very large array of processors can be constructed. The array could be mounted in a single VME enclosure, or it could span multiple enclosures for complex systems such as sonar or Synthetic Aperture Radar (SAR).

While these large systems are functionally sound, there is yet another alternative waiting in the wings ready to bring about a return to the hybrid architectures of earlier DSP systems, but with major savings in real estate and overall system cost. In a typical system, the initial front-end filtering and processing (decimation and FFT) would ideally be performed by hardware as these are repetitive established algorithm operations. However, this has been prohibitively expensive for small volume production, and especially prohibitive in the case of multiple channel applications. The advent of RAM-based Field Programmable Gate Arrays (FPGAs) such as the Xilinx Virtex-II Pro family, with as many as 100,000 logic cells, multipliers, and internal RAM, clocking at 400 MHz+ swings the economic pendulum back towards a front-end hardware solution. Unlike a PowerPC or dedicated DSP processor, an FPGA can be designed to perform multiple operations in parallel on an incoming data stream. Previously, this kind of parallelism required a large number of PowerPCs with the attendant data distribution issues. This issue is easily solved if all of the PowerPCs are located on a single VME card, but the solution is much more complex if the data is spread across a number of cards or racks. Because an individual PowerPC will generally process the data from a sensor source serially and has to rely on switched fabrics for rapid data movement, there is often a need for additional design margins to cope with a reduced level of determinism. FPGAs, being logic-based, operate deterministically and do not require the overhead of frequent synchronization. The use of FPGAs in the critical front-end can result in substantial cost savings on the order of 10x PowerPCs.

An FPGA such as the Virtex-II Pro also has a number of dedicated very high speed I/O channels, for example, RocketIO running at 3 GHz+ to input sensor data at high speed as well as being used to transfer blocks of data from one FPGA to another. In addition, the Virtex-II Pro contains PowerPC cores that could be used for more of the generic processing functions using all the traditional PowerPC development tools for support. The in-situ reprogrammability of the FPGA also allows for adaptive algorithms that could, for example, adopt different DSP configurations depending on the operating mode required of a sensor. An example of this might be a multi-mode radar that is equally effective at long range surveillance and very short range weapons direction against multiple threats.

It would then seem that FPGA-based DSP is set to displace the front-ends of the large and complex systems in use today, making VMEbus and COTS products redundant. After all, FPGAs are single devices. Does this point backwards to the reintroduction of proprietary architectures with all their attendant development, maintenance, upgrade, and sustainability risks? To do so would be to ignore the huge investment legacy in the infrastructure and architecture of VME and all its complementary standards that have made current systems so powerful and reliable, particularly in harsh environments that require conduction cooling and resistance to the effects of shock and excessive vibration. It is also very unlikely that a complete sensor system such as a radar or sonar could be constructed exclusively from FPGAs. There is a significant amount of general-purpose processing that still has to be performed on the data streams before any meaningful interpretation or defensive/offensive reaction can be taken, e.g. targets must be identified and classified, threats evaluated, and weapons/evasive systems deployed. All of these defensive/offensive reactions will be initiated by decision makers who require the use of significant logical and decision-based processing and information sharing applications. These applications are ideal for general-purpose, embedded computers such as the PowerPC.

Even though very few of today's DSP systems actually make use of the VMEbus itself, they rely on the wealth of VME standards and the industry's product base for their infrastructure, support, interconnect, packaging, and network fabrics. Often VME is only used for system initialization, self-test, and management using a general-purpose SBC in slot 1 of the chassis, while dedicated I/O, PCI, and switched fabrics are used for the DSP application. New FPGA-based DSP products are now being introduced into this infrastructure and support environment. A 6U VME card can accommodate two or more FPGAs, a large complement of 64-bit and 128-bit DDR and DDRII SRAM, two PMC/XMC sites, a local PowerPC controller, and a pair of switched fabric interconnects. RocketIO ports will be used to connect to the sensor digital data streams, to pass data between the onboard FPGAs, and to provide external links to other FPGA cards. Products are now available from several defense and aerospace-focused vendors who provide complete system-level solutions which connect FPGA front-ends to existing multiple PowerPC processor products via their preferred switched fabrics, e.g. Mercury Computers with Race++ fabric interconnect, and Dy 4 Systems with StarFabric. As an example, the Dy 4 Systems CHAMP-FX DSP board which incorporates two Xilinx Virtex-II Pro FPGAs for digital signal processing is shown in Figure 1.

Figure 1: Dy 4 Systems CHAMP-FX DSP board, including two Xilinx Virtex-II Pro FPGAs for digital signal processing

Interestingly, the introduction of fully supported FPGA-based products for DSP applications might cause a further convergence between hardware and software development engineers. Is an FPGA a piece of hardware or software and to which discipline does it belong during its development? The use of development tools and libraries is likely to be the discriminator, with logical and embedded tools to be used by hardware engineers, while graphical/mathematical tools such as MATLAB to be used by software and systems engineers.

The use of proven infrastructure and architecture to incorporate FPGAs into a new or upgraded DSP system is key to implementing a successful and economical solution.

VITA recognized the need to incorporate many of the features required for these new DSP solutions in the development of standards such as VITA 34, 41, and the recently announced VITA 46. VITA 46 will offer radical new capabilities for VME systems deployed in harsh environments with support for multiple switched fabrics, improved I/O connectivity, and the support of Gbit+ signaling rates through the backplane connectors. These connectors can be used for high-end radar, sonar, graphical, and digital radio DSP applications. Applications such as the radar system used on the AWACS aircraft (Figure 2) will employ FPGA-based DSP solutions.

Figure 2: Airborne Warning and Control System (AWACS) aircraft

The FPGA has become a key component in the battle to increase the sensitivity and performance of sensor systems while reducing cost, power, and space requirements. As usual, VME and its infrastructure have evolved to remain the ideal platform for implementation thereby encouraging migration from existing systems, and the development of new systems.