Fabric speed and I/O bandwidth: Performance for next-generation military systems
In the not-too-distant past, advanced compute-intensive military systems required custom hardware and software solutions. Because of the tremendous increase in embedded computing performance from continuing advancements in processor architectures, open standards platforms are taking the lead. The evolution of process geometries has also brought innovations that continually improve the performance-per-watt equation that greatly helps designers achieve SWaP requirements. Performance per watt has improved almost 400 percent since 2003, comparing the Pentium M at 1.6 GHz to today’s Intel Core i7 at greater than 3 GHz. But designers have been challenged to match the I/O bandwidth level required to unleash the massive increase in parallel embedded computing that is now available.
Rugged, high-performance computing improvements from VPX (VITA 46) – and its system-level interoperability progeny OpenVPX (VITA 65) – help solve design challenges in terms of enclosure, backplane, and computer management and enhanced programming models. These technological advantages are needed by a broad range of next-generation, high-performance embedded military applications such as UAVs, ground vehicle sensors, countermeasure systems, radar systems, and hyperspectral imaging. At the heart of these improvements are new fabric interconnects that enable enhanced levels of subsystem application performance.
The need for speed
Designers benefit in the switch from VME to VPX and OpenVPX in terms of interconnect fabric speed. VME backplane communications are limited to 1 GbE bandwidth. Access to higher-performance technologies including Serial RapidIO, 10 GbE, and PCI Express is available thanks to OpenVPX connector and backplane design. These serial high-speed backplanes allow full bandwidth between each board, and point-to-point routing is fixed. The interconnect CPU bandwidth offered by VPX facilitates adding these new higher-speed, industry-standard technologies to be implemented at the board level.
OpenVPX backplane design saves costs and development time as well. Costs are reduced as the need for a specialized data-transmission mezzanine that allows the exchange of data from board to board with front-end cables will no longer be necessary. Development time is shortened because the core chipset now delivers high-speed I/O on the backplane and doesn’t require specific device driver development. For example, PCI Express support comes by default with the latest generation of Intel bootstrap processors.
Designing high-performance military systems is more streamlined with standardized OpenVPX interconnects that access the latest high-speed technologies. Accessible bandwidth at more than 3 Gbps helps designers build a more balanced system. Plus, serial full-mesh backplane interconnects permit full bandwidth between each board with fixed point-to-point routing.
In addition, fabric protocol compatibility is no longer an issue. With VPX-based boards, the backplane technology, the signal allocation, and voltage on the backplane are the same regardless of the final choice of fabric technology. This gives designers greater flexibility to add different types of I/O directly into the fabric.
Preconfigured backplanes support higher bandwidth
OpenVPX standards define preconfigured payload backplanes in an effort to accommodate higher-bandwidth needs. 3U and 6U form factor OpenVPX backplanes are available in lengths between 1 and 21 slots. Designers have two types of backplane families from which to choose:
1. Centralized – defines separate payload and switch management slots so the system can be fitted with a switch board. Switch boards can be either data-plane switches that support 10 GbE, Serial RapidIO, or PCI Express, or control plane switches that support 1 GbE.
2. Distributed – defines a direct connector backplane for smaller system implementations. The length between slots is prearranged, allowing for a more compact system design.
Putting OpenVPX backplanes to work
Allowing next-generation radar applications to see farther and implement new algorithms to extract useful information from the clutter requires the ability to process an immense amount of data. This puts a ten-fold increase on the demand to the backplane compared to radar systems deployed today. An example of an optimal OpenVPX interconnects solution for radar systems is a new 6U VPX-based blade. VPX blades are now available with two independently implemented processing nodes that are linked to a powerful Ethernet and PCIe infrastructure. Embedding two dual-core, high-performance embedded processors provides a viable solution for applications where the power envelope and dissipation constraints at extreme temperatures still prohibit the use of quad-core silicon. High-performance VPX blades are ideal building blocks that support 10 GbE for intensive parallel computing workloads frequently required for radar systems, and can be deployed as a full mesh or switched network.
Meeting today’s design requirements
The value of OpenVPX interconnects to military systems designers is that they leverage a powerful backplane infrastructure to develop high-performance applications that use standard technologies such as Linux or RTOS on well-known x86 architectures that ensure future scalability. The I/O bandwidth supplied by two independent Single Board Computers (SBCs) in a single 3U or 6U VPX slot gives the performance needed for compute-intensive military applications such as radar, sonar, and other rugged systems. And, as newer standards are needed or defined, OpenVPX has the built-in flexibility to evolve and include new fabric, connector, and system technologies.