Bringing the programmable imperative to space

Suddenly space is the place, where most people think of space ships, the Space Shuttle, and Star Trek. But the reality is that most of the world’s efforts in space tech are invested in only one area: Satellite Communications (SATCOM). And with more of the world squawking on the Internet using VoIP for voice, SATCOM is the WAN of choice for long-haul, geo-distant communications. To meet the exponentially growing SATCOM bandwidth demand, providers are using smart technology instead of just adding fatter pipes. Usually, this means adding routers, deep packet inspection, and Software-Defined Radios in the satellite “bird” itself, subject to the harshness of space.

During an interview a couple of years ago [] with Boeing’s Roger Krone, then-president of Network & Space Systems (N&SS), I quipped, “Surely you don’t have the same [network communications] technology found in a Cisco router?” Dumb question, because Boeing’s Spaceway 3 actually does have a 10 Gbps capacity router, a dozen ASICs at 10 million gates apiece, and technology-sharing partnerships with both IBM and Cisco. In fact, Boeing’s nearly $1 billion contract from the USAF for Transformation Satellite Communications (TSAT) incorporates Cisco’s proprietary terrestrial algorithms for in-space network packet routing. My point: The high-tech stuff that runs the Internet on Earth is also flying in space. VME has been used in the past; OpenVPX is being designed with FMC mezzanines using FPGAs and ASICs for key functions.

But satellites are different from wiring closets: They’re too far away to service, launch weight is at a huge premium, and the radiation effects of low-Earth and geosynchronous orbit eliminate using COTS components without radiation mitigation strategies to protect against the soft errors of Single Event Upset (SEU) or Single Event Transient (SET). As well, programmability – in both software and hardware logic – is now a mandated characteristic to remotely add new features and fix unforeseen logic problems.

Interestingly, both Mentor Graphics and Xilinx recently introduced new FPGAs and EDA tools intended for radiation-hardened designs in SATCOM. Yet they are taking wildly different approaches to dealing with SEU and SET. Which is best? That’s up to your radiation effects scientist.

Mentor Graphics, of course, is an EDA company selling tools for simulation, synthesis, and PWB designs. The company’s new Precision Rad-Tolerant FPGA design tool is meant for FPGA and ASIC A&D designs like SATCOM where vendor independence and automated mitigation are desirable. Huh? This means that designers aren’t forced to use Actel’s or Xilinx’s design tools or special (read: expensive!) rad-hard silicon. Designers also don’t need to hand code special mitigation logic in HDL because Precision Rad-Tolerant can automatically add logic during synthesis.

Mentor Graphics’ tool is pretty cool because it uses fault-tolerant Finite State Machines (FSMs) that can “absorb” radiation-induced SEUs, thereby mitigating radiation particles’ effects on transistors. Developed under NASA’s guidance, in addition to FSMs there’s traditional Triple Modular Redundancy (TMR) that can also be instantiated in the logic. Precision is smart enough to only “triplicate” the most common signals used for TMR, rather than just blindly trebling all sensitive logic. This saves silicon, power, and complexity – as well as design time because it’s all built into the synthesis program. As I mentioned, the tool provides vendor-independent techniques, unlocking long life-cycle VME designs from any specific FPGA or ASIC vendor/foundry.

Xilinx also sees a chance for new business in A&D, which is a segment buried in the company’s 32 percent of revenue “Industrial and Other” marketing breakout. Xilinx is expecting radiation ICs to represent about 10 to 20 percent of their A&D business (which is some TBD percentage of that 32 percent). But unlike Mentor, Xilinx has introduced the Virtex-5QV, a silicon-hardened FPGA that runs at a whopping 450 MHz, has 130,000 logic cells, and sports 3.125 GHz RocketIO transceivers (Figure 1).

Figure 1: Unlike Mentor, Xilinx has introduced the Virtex-5QV, a silicon-hardened FPGA that runs at a whopping 450 MHz, has 130,000 logic cells, and sports 3.125 GHz RocketIO transceivers
(Click graphic to zoom by 1.4x)

If you’re old like me, you’ll remember the former “Class S” ICs from the MIL-Q-38510 and MIL-STD-883 mil specs, which were designed and extensively screened to assure rad-hardness. In fact, SEU and SET mitigation was “by design.” Similarly, Xilinx believes they have the first COTS in-space reconfigurable FPGA capable of reaching 700 KRad(Si) with no extra mitigation via TMR, scrubbing, or other means. I believe them. This contrasts with the company’s equivalent mil-temp FPGA that on a good day might achieve 300 KRad(Si) with substantial mitigation logic and a few late-night prayers by the radiation architect.

The huge XQRVFX130 – one of the new QV family – has SEU latch-up immunity to 100 MeV-cm2/mg at under 10E-10 upsets/bit-day. The device is built on the company’s same 65 nm technology but incorporates additional (and unspecified) logic and transistors to achieve off-the-shelf radiation mitigation. It’s also programmed via Xilinx standard ISE tools.

So which approach is better for rad-hard SATCOM? If you’re using a Xilinx device already and can pay the roughly 100x (estimated) premium over the commercial V-5, buy the QV device. If you want cheaper silicon, have the Mentor tools already, or want vendor independence, go for Mentor’s Precision Rad-Tolerant tool. Let me know what you decide.

Chris A. Ciufo