Bringing LTE to OpenVPX
Reliable communications are critical in defense applications, and the ability to set up ad hoc networks where existing communications are absent or damaged is key to future combat systems. When assessing the next generation of technology with which to upgrade existing military communications infrastructure, it's difficult to ignore standards-based solutions such as Long-Term Evolution (LTE) systems.
These standards are developing at such a pace that their data transfer performance is already an order of magnitude greater than that of technologies developed purely for tactical communications, such as the Joint Tactical Radio System (JTRS)1. Since LTE uses Internet Protocol (IP) for data transmission, radio security can be achieved from packet encryption technologies rather than developing a secure radio network, such as the Wideband Networking Waveform (WNW) used by the JTRS2.
And the widespread deployment of civilian LTE networks means a proliferation of field-hardened LTE solutions. With that background, the appetite for developing a proprietary military radio network has gone and JTRS was terminated.
LTE is a mature technology, and a large selection of commercial off-the-shelf (COTS) solutions already exists for base stations, user equipment (UE), and wireless test. It makes sense, then, that a move to LTE-based networks is also accompanied by a move to COTS-based solutions.
The ruggedized requirements for military systems require open standards COTS architecture that is up to the task. OpenVPX (VITA 65.0) is a widely adopted VPX-based standard which builds on the great success VME systems have had in this arena. The VPX-REDI specifications of VITA 48.0, with conduction-cooled and air-cooled versions, provide the assurance of mechanical ruggedization in COTS-based military systems. These specifications also deliver on size, weight, and power (SWaP) limits3.
Being an open standard, component cards are available from an ecosystem of suppliers. This helps multi-sourcing, and means that a range of chassis architectures is available to suit different deployed scales and architectures. For example, developments can begin on the bench with 6-slot air-cooled systems and then migrate to 12-slot 19" rack equipment or conduction-cooled ATR solutions while using the same plug-in card architectures.
Ruggedizing COTS solutions
One of the major challenges in supporting the VPX-REDI specification is the move from field-proved non-rugged systems to the OpenVPX conduction-cooled architecture. This is one of the challenges we are addressing today.
For example, the CommAgility AMC-D24A4-RF4 is a double-width AdvancedMC (AMC) card comprising a wireless baseband processing carrier card and RF mezzanines. Aimed at the LTE and LTE-Advanced wireless test market, but also finding use in small captive base stations, this architecture is a great fit for rapidly deployable military communications.
Our task was to adapt this card for rugged VPX deployment. By looking at the design issues faced, and the choices made, we can explore the challenges faced by any COTS manufacturer in bringing LTE to VPX, and the factors that a customer should consider when reviewing vendors’ products.
The first challenge addressed has been the creation of a VPX-REDI baseband processing card. The VPX height profile limits the use of mezzanine-based solutions where power dissipation is high, and in this case led to the architecture being laid out on a single baseboard. This was achieved by making use of an increased Side 2 height profile in comparison to AMCs, thus allowing memory devices to be placed on Side 2. The VPX specification also supports the use of PCBs with more layers, which makes device fan-out easier and supports a higher density of components on Side 1.
The next task was the conduction cooling clamshell design that could achieve the required -40 °C to +85 °C operational range. Fortunately, the maturity of the VPX standards means that component parts, such as the card guides, of a conduction-cooled solution were readily available off the shelf. A custom heatsink could then be created based on thermal profiling of the card and incorporating the card guides.
Backplane mapping within the OpenVPX chassis is also important. Although governed by a set of pre-determined slot profiles within the specification, a wide variety of backplane architectures have been implemented. A base backplane configuration was identified, with the 2F2U configuration of a pair of ultra-thin control pipes and two fat pipes for fabric connection.
The VPX-D16A4 supports build options for both RapidIO fabric connectivity and PCIe connectivity (see Figure 1). This is required to address the two main architectures supported by the card. RapidIO is required for its low latency in wireless applications where digital radio data is being transported on the backplane. However, PCIe is important where the digital radio data is being generated by the baseband card from Layer 3 data provided by a general-purpose processor card in the system, typically using an Intel device where RapidIO is not natively supported.
The user-defined areas of the P1 connector were then allocated for high-speed point-to-point wireless communication with an RF card in the same chassis, or potentially a custom rear transition module (RTM). The DSPs support CPRI direct connection to these ports from its antenna interface (AIF).
The FPGA supports P1 user-defined connections to its high-speed transceivers. These transceivers are also capable of implementing a CPRI interface, but can additionally support the JESD204B protocol now widely being deployed as an interface for data converters. As well as supporting JESD204B, the P2 connector has been defined to support RF processing cards supporting a LVDS data interface. Usually this is implemented as a synchronous DDR interface, with the clocks provided with the data bus.
Support for a 10 Gigabit Ethernet (GbE) interface direct from the ARM-enabled DSP is provided by a native XFI interface. Where the baseband card is processing Layer 3 wireless data, 10 GbE is an important data path for wireless backhaul.
Towards an RF front end
The next challenge we are addressing is the integration of an RF front end into the same ruggedized VPX chassis. Let’s examine some of the issues around such an integration, and some possible solutions.
Digital backplane connectivity
To add an RF front end to the solution requires support for the necessary digital wireless bandwidth to the baseband card, determined by a combination of antenna diversity and data bandwidth. Higher bandwidths may dictate a JESD204B interface on the wireless transceiver rather than LVDS. Since the RF card is designed to act in tandem with the baseband card the backplane connectivity should be complementary.
Backplane architectures could support JESD204B or LVDS natively between the wireless transceivers and the baseband card. More generally, however, a local FPGA is used for flexible connectivity, allowing additional low latency interconnects such as RapidIO to be used. The VPX-D16A4, for example, supports two 20 Gbps RapidIO fat pipes, which can also be used to connect to an RF card.
The RF card must also support control of the RF transceivers, including channel switching for time-division duplex solutions, and handling the digital up and digital down conversion (DUC/DDC) required to support multiple sub-channels in the RF channel. This role usually falls to an FPGA device acting as a control processor, which then also needs to be connected to the VPX control plane for card management.
RF backplane connectivity
Having defined an approach to support digital radio data transport across the backplane, a method is required to transport the analog RF data from the card to an external chassis interface.
Air-cooled solutions can use a traditional front panel RF connector on a VPX card, with a cabled solution from the chassis to the enclosure panel. Mounting the chassis with the front panel towards the rear of the enclosure allows the cabling to be kept neatly out of the way. However, this is not conducive to servicing the cards, which requires a re-cabling of the enclosure and can’t be supported by conduction-cooled solutions.
This is one of the reasons VITA 67.0 “Coaxial Interconnect for VPX” has been developed. By supporting backplane co-axial connectivity, front cards can be quickly swapped in and out of the chassis and there is no reliance on front panel I/O in a conduction-cooled environment. Using semi-rigid cabling from the analog RF section of the card to the VITA 67.0 connectors minimizes the RF loss and noise on the card (see Figure 2).
As military comms and secure radio applications continue to adopt commercial radio standards for the air interface, there exists an opportunity for COTS-based platforms developed for the commercial world to migrate to more ruggedized platforms. This is not without its challenges. Conduction cooling and SWaP consideration place additional constraints on equipment originally designed for the central office environment.
However, OpenVPX is an ideal framework on which to achieve this. It has a mature base standard with an ecosystem of off-the-shelf building blocks, yet is flexible enough to introduce innovations such as backplane co-axial interconnect to address real-world problems. This combination of field-proven technology and foresight make OpenVPX a standard with a future.
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