# Using a mesh FPGA architecture to implement adaptive beamforming radar

### Beamforming applications such as radar and sonar can be greatly enhanced, scaled, and revved up to higher performance with FPGAs interconnected via the VITA 41.7 VXS mesh architecture.

Beam forming applications such as radar and sonar can be greatly enhanced, scaled, and revved up to higher performance with FPGAs interconnected via the VITA 41.7 VXS mesh architecture.

Building an FPGA mesh architecture allows the scalable implementation of algorithms such as adaptive beamforming radar. By building a fully functional system using FPGAs for processing that is interconnected via the proposed VITA 41.7 VXS Processor Mesh architecture, the system can be scaled to address larger number of receiver channels. This architecture also allows for faster weight calculation, resulting in a higher-performance system.

Digital signal processing for adaptive beamforming radar has three principal subsystems (Table 1):

- The digital receiver for each channel, which includes: Sensitivity Time Control (STC), digital downconversion and bandlimiting filtering (DDC/FIR), and range gating
- Adaptive Weight Calculation (AWC) for determination of the coefficients for adaptive beamforming
- Adaptive BeamForming (ABF), using the coefficients calculated

Figure 1 shows the adaptive beamforming system architecture:

There may be several beams required – for example, a sum-beam, azimuth beam, and elevation beam. This requires a separate AWC and a separate ABF for each beam. These calculations are independent and can be computed concurrently.

The rate at which the AWC operation can be performed determines the adaptation rate of the radar and hence the ability to react to rapidly changing environments including: target motion, clutter/jammer motion, and radar platform ego-motion. Therefore it’s desirable to reduce the latency of the AWC operation as much as possible.

FPGAs are a suitable implementation technology for adaptive beamforming radar because they:

- Can process data in real time as it is streamed from the ADCs, which digitize each radar receiver channel’s IF output
- Can operate at appropriate arithmetic word lengths to maximize processing capability and achieve the necessary system SNR requirements
- Are a highly efficient implementation technology in terms of size, weight, and power versus general purpose PCs
- Provide a scalable implementation platform. A mesh architecture provides a highly interconnected array of FPGA compute resources, allowing the DSP algorithm to be distributed over a large number of devices for high throughput

A suitable approach to implementing AWC in FPGA technology is to undertake the processing in the data domain via QR decomposition, a linear algebra technique of decomposing the matrix into an orthogonal and a triangular matrix. This approach has been shown to be more suitable for FPGA implementation and more robust to reduced numerical precision, such as word lengths, than the conventional covariance domain approach, which requires high numerical precision to effectively perform a matrix inversion.

By mapping the triangular QR array onto an array of linearly interconnected processing units, a scalable architecture is obtained that can be implemented on a set of linearly interconnected FPGAs. In order to reduce the processing latency of the QR operation, more rotate operators can be added to the mapping by extending the linear array.

The QR operation is replicated for each of the beams that must be formed. Constraints are applied to each QR operation, for example, to determine the beam pointing direction. These are updated each time the AWC operation is carried out.

Beamforming is a spatial filter that forms a weighted sum of the data from each receiver channel. The weights are provided by the AWC operation and remain constant within a weight update period as shown in Figure 2. There is a separate beamformer for each of the beams to be created. In this implementation, the accumulation of all channels is distributed across several FPGAs.

Figure 2: Schematic of the beamformer subsystem. The accumulation of all channels is distributed across several FPGAs. |

**Implementation on a mesh architecture**

As shown in Figure 3, the front end digital receiver DSP is implemented in a column of FPGAs. Each FPGA accommodates the DSP for a number of receiver channels determined by the available input bandwidth and the available FPGA resources. For example, a single 105 MSps, 14-bit ADC produces a raw data rate of 1.5 Gbps, so a budget of one 2.5 Gbps high-speed serial link per ADC channel comfortably allows for any protocol and other overheads. These FPGAs may be located on the ADC digitization cards, in which case they would form inputs to the mesh, rather than being part of the mesh.

Each QR processor occupies one column of FPGAs. In the mesh architecture, a column of FPGAs is implemented on a single board, so the FPGAs may be more closely coupled than just with the high-speed serial links. The QR operator can exploit this by using a high-bandwidth daisy chain parallel bus to interconnect the rotate cells on adjacent FPGAs. If a single column of the mesh does not provide sufficient processing resources to implement the QR operation with the required processing latency, then the QR operation may be distributed over two or more columns.

All of the beamformers are implemented in a final column of FPGAs. The beamformer is a simple architecture (see Figure 4), requiring only one complex multiplier per receiver channel and an adder chain to accumulate the results from all channels. The adder chain is distributed down the column, so the beamformed results are available from the bottom FPGA in the column. Note: Figure 4 represents the same architecture as Figure 3, but with additional comments to help the reader’s interpretation.

The bottom row of FPGAs in the mesh provide a control interface to the DSP architecture, as well as implementing the back-substitution operation required within each QR operation. This is most efficiently implemented using a microprocessor; in the case of Xilinx Virtex-II FPGAs, this can be done with the on-chip PowerPC core. The weights are generated directly from the back-substitution operation and are passed to the beamformer for application to the receiver data. If FPGA resources permit, the control and back-substitution function could be combined with the bottom row of DSP operation, allowing a smaller mesh to be used or more receiver channels to be implemented.

**Future of beamforming**

Scalable implementations of algorithms such as ABF are ideal for implementation on a VXS Processor Mesh architecture**.** This type of implementation removes the constraints of working within a single FPGA. A balance between inter-FPGA communications bandwidth and FPGA processing resource removes a scalability bottleneck. This allows the mesh architecture to be scaled to address a larger number of receiver channels or facilitates requirements for faster weight calculation.